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Tanner S-Edit

芯片原理图设计软件

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<p><span style="color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; text-wrap: wrap;">Tanner S-Edit 是一个面向原理图输入和设计的易于使用的开发环境。它为您提供处理最复杂的混合信号 IC 设计所需的功能。S-Edit 与 Tanner T-Spice、Analog FastSPICE™ (AFS) 或 Eldo® 仿真器、Tanner™ L-Edit IC 版图工具以及 Calibre® LVS 和 PEX 工具紧密集成。S-Edit 可通过优化提高您的生产率并加速概念到芯片的转换，帮助您满足当今快节奏的市场需求。更快的设计周期使您可以更灵活地转向优化的解决方案，为工艺角验证腾出更多的时间和资源。最终可降低下游风险，提高良率并缩短上市时间。</span></p>
Tanner S-Edit Schematic Capture

芯片原理图设计软件

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<p><span style="font-size: 12px;">Siemens Digital Industries Software helps speed up mixed-signal IC design capture<br/><br/><br/><strong style="font-size: 12px; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica;">Benefits</strong></span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•Handles your most complex, full-custom IC schematic capture</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•Integration with AFS. Symphony, and Eldo simulators, allowing waveform cross-probing and direct viewing of operating point simulation results in the schematic</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•Export formats: SPICE, EDIF, Verilog and VHDL</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•Import formats: Native OpenAccess, EDIF, SPICE and Verilog</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•Support for inherited connections</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•Cross-probe between schematic, layout and Calibre LVS report with net/device highlighting</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•Configurable schematic Electrical Rule Checks (ERC)</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•Multiple-views per cell including: SPICE, schematic, Verilog, Verilog-A and Verilog-AMS views</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•Advanced array and bus support</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•Integrated with Tanner L-Edit Schematic Driven Layout (SDL) module to speed the layout and ECO process</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">• Multiple library support with integrated library browser</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">• Fully scriptable and expandable using TCL/Tk command language</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">• Offers easy interoperability with third-party tools and foundry PDKs</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">• Platform independence on Windows or Linux</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">• Ease of use: intuitive and quick learning curve</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">• Unparalleled customer support</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">• Flexible licensing</span></p><p><span style="font-size: 12px;"><br/></span><br/></p>

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