YAENTEK雅恩信息·SiemensEDA软件授权代理商|PADS|Xpedition|Modelsim|Hypeylynx|Valor|Flotherm|KeilMDK|天瑞绿盾|微软|Office|CAM350代理商

Xpedition Substrate Integrator

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<p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;"><strong>Benefits</strong></span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•Rapid hierarchical planning, prototyping and optimization of 2.5/3D heterogeneous assemblies</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•System connectivity management and visualization with cross-domain pin/signal mapping/shorting and system-level logical verification</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•User-definable rules for custom optimization of pin and ball-out assignments</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•System-level predictive SI/PI</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•Predictive data path flow planning</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•System Verilog integration</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•50M+ pin design support</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•Extensive input and output data formats</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•System-level LVS/STA verification through Calibre® 3DSTACK</span></p><p style="margin-top: 5px; margin-bottom: 5px; overflow-wrap: break-word; color: rgb(0, 0, 0); font-family: "sans serif", tahoma, verdana, helvetica; font-size: 12px; text-wrap: wrap; line-height: 32px;"><span style="font-size: 12px;">•Direct integration with Xpedition Package Designer for detailed implementation</span></p><p><br/></p>
Xpedition Package Designer

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<p><span style="font-size: 16px;">Xpedition Package Designer高级封装 (HDAP) 设计软件</span></p>

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